The subject matter disclosed herein relates to charge-to-digital conversion devices and, in particular, to charge conversion performed by capacitance-based integrate-and-fold circuits.
X-ray imaging systems typically include sensor systems that transform attenuated analog x-ray signals into electronic form. The imaging system may include a data acquisition section for converting the analog signal in electronic form into a digital output signal that can be read by other digital processing elements. For imaging-based applications, this conversion process benefits from low-noise and high-dynamic range signals that can be converted at frequencies from about 500 Hz to about 100 kHz. Conventional charge-to-digital conversion circuits typically use an integration capacitor with an operational amplifier (i.e., op amp) to produce an output signal that is a function of an input charge produced by the x-ray signal. As can be appreciated by one skilled in the art, a relatively large integration capacitor may be required if the analog input signal has a relatively large range.
For example, charge to digital conversion can be accomplished via a conventional analog-to-digital conversion (ADC) circuit 10, shown in FIG. 1, which uses an amplifier with an integration capacitor and a current-mirror-based folding (or subtraction) unit to perform current folding, as disclosed in U.S. Pat. No. 6,366,231 “Integrate and fold analog-to-digital converter with saturation prevention.” The ADC circuit 10 comprises an input signal circuit 12 in electronic communication with an integrate-and-fold circuit 20. The integrate-and-fold circuit 20 includes a folding circuit 30, an integrating op amp circuit 32, and a digital logic circuit 34. During operation, an analog input signal 26 is transmitted by the input signal circuit 12 to the inverting input terminal of an operational amplifier 18 in the integrating op amp circuit 32, which stores a charge proportional to the integral of the analog input signal 26. The digital logic circuit 34 functions to determine when the charge level in the integrating op amp circuit 32 reaches a predetermined value.
In an alternative method of current-based folding, shown in FIG. 2, a circuit 40 includes an integration circuit 42 to provide an analog current signal via a fold switch 44 to the inverting input terminal of the operational amplifier 18, where the non-inverting input terminal is attached to ground. An analog output signal is provided to a sample-and-hold circuit (not shown) at the output terminal of the operational amplifier 42. Both the current-folding methods illustrated in FIG. 1 and FIG. 2 perform charge subtraction from an integration capacitor 28 (CINT) in accordance with current multiplied by time (i.e., Q=I*t).
When this charge value is reached, the digital logic circuit 34 in FIG. 1 directs the folding circuit 30 to remove a predetermined quantity of charge from the integration capacitance 28 in the integrating op amp circuit 32. This discharging process is repeated as the charge level in the integrating op amp circuit 32 is replenished, and the digital logic circuit 34 functions to keep track of the number of times the predetermined charge quantity is removed from the integration capacitance 28. After a predetermined time interval, the digital logic circuit 34 determines an output signal based on the number of discharge operations performed by the folding circuit 30. The output signal also includes any residual charge quantity remaining in the integrating op amp circuit 32 that is supplied to a sample-and-hold circuit 24.
The bits resolved by the digital logic circuit 34, along with the additional bits resolved from the residual charge quantity, can be used to provide a binary output signal. By serially removing the charge quantities from the integration capacitance 28, the integrating op amp circuit 32 can thus accommodate a larger analog input signal than could otherwise be stored by the integration capacitance 28 alone, and can thus maintain a relatively large dynamic range of voltages in the ADC circuit 10.
A multi-channel analog-to-digital conversion circuit is disclosed in U.S. Pat. No. 7,095,354 “Very linear wide-range pipelined charge-to-digital converter,” in which a current processing stage is used to perform current-based folding and a subsequent voltage processing stage is used to further process analog residual from a previous stage.
The inventors herein have recognized a need to perform analog-to-digital conversion in modern imaging systems having a dynamic range requirement of six orders of magnitude or greater.